314 search results - page 8 / 63 » Reducing Parallel Overheads Through Dynamic Serialization |
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
PDP
2008
IEEE
14 years 1 months ago
2008
IEEE
Matrix computation algorithms often exhibit dependencies between neighboring elements inside loop nests such that the frontier between computed elements and those to be computed w...
ICIP
2006
IEEE
14 years 1 months ago
2006
IEEE
—In this paper, we propose multiple tree construction schemes and routing protocols for video streaming over wireless ad hoc networks. The basic idea is to split the video into m...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Programs with irregular patterns of dynamic data structures and/or those with complicated control structures such as recursion are notoriously difficult to parallelize efficient...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...