9 search results - page 1 / 2 » Reducing wire delay penalty through value prediction |
MICRO
2000
IEEE
13 years 12 months ago
2000
IEEE
In this work we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating...
ICS
2004
Tsinghua U.
14 years 28 days ago
2004
Tsinghua U.
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
ICCAD
2003
IEEE
14 years 25 days ago
2003
IEEE
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...
DAC
2003
ACM
14 years 24 days ago
2003
ACM
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...