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ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
14 years 1 months ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
BIRTHDAY
2004
Springer
14 years 1 months ago
Two Models for Gene Assembly in Ciliates
Two models for gene assembly in ciliates have been proposed and investigated in the last few years. The DNA manipulations postulated in the two models are very different: one mode...
Tero Harju, Ion Petre, Grzegorz Rozenberg
ICALP
2004
Springer
14 years 1 months ago
A Calculus of Coroutines
We describe a simple but expressive calculus of sequential processes, represented as coroutines. We show that this calculus can be used to express a variety of programming languag...
James Laird
IJCNLP
2004
Springer
14 years 1 months ago
Iterative CKY Parsing for Probabilistic Context-Free Grammars
This paper presents an iterative CKY parsing algorithm for probabilistic contextfree grammars (PCFG). This algorithm enables us to prune unnecessary edges produced during parsing,...
Yoshimasa Tsuruoka, Jun-ichi Tsujii
ICNP
2002
IEEE
14 years 27 days ago
Power Mode Scheduling for Ad Hoc Networks
An ad hoc network is a group of mobile wireless nodes that cooperatively form a network among themselves without any fixed infrastructure. Increasingly, power consumption within ...
Santashil PalChaudhuri, David B. Johnson