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» Reduction of Timed Hybrid Systems
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HOTI
2008
IEEE
15 years 10 months ago
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly popular interconnection fabric due to their ability to supply high bandwidth. However, NoCs...
Tushar Krishna, Amit Kumar 0002, Patrick Chiang, M...
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
15 years 9 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
111
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LCTRTS
2004
Springer
15 years 9 months ago
Link-time optimization of ARM binaries
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded ...
Bruno De Bus, Bjorn De Sutter, Ludo Van Put, Domin...
LCPC
1994
Springer
15 years 8 months ago
Optimizing Array Distributions in Data-Parallel Programs
Data parallel programs are sensitive to the distribution of data across processor nodes. We formulate the reduction of inter-node communication as an optimization on a colored gra...
Krishna Kunchithapadam, Barton P. Miller
FAST
2003
15 years 5 months ago
Using MEMS-Based Storage in Disk Arrays
Current disk arrays, the basic building blocks of highperformance storage systems, are built around two memory technologies: magnetic disk drives, and non-volatile DRAM caches. Di...
Mustafa Uysal, Arif Merchant, Guillermo A. Alvarez