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» Redundancy in Instruction Sequences of Computer Programs
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DSN
2002
IEEE
14 years 1 months ago
Detecting Processor Hardware Faults by Means of Automatically Generated Virtual Duplex Systems
A virtual duplex system (VDS) can be used to increase safety without the use of structural redundancy on a single machine. If a deterministic program P is calculating a given func...
Markus Jochim
ITICSE
1999
ACM
14 years 27 days ago
A multimedia animated simulation generator
This paper shows how a multimedia multi-framed simulation generator was developed. A technique of recording a sequence of steps and playing them back as an animation overcomes the...
John Hewson, Wendy Doube, Michael Calagaz
IWOMP
2007
Springer
14 years 2 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
TJS
2002
160views more  TJS 2002»
13 years 8 months ago
Adaptive Optimizing Compilers for the 21st Century
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...
Keith D. Cooper, Devika Subramanian, Linda Torczon
ICS
2003
Tsinghua U.
14 years 1 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman