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IPPS
2007
IEEE
14 years 1 months ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas
IPPS
2000
IEEE
13 years 11 months ago
A Mechanism for Speculative Memory Accesses Following Synchronizing Operations
In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following ...
Takayuki Sato, Kazuhiko Ohno, Hiroshi Nakashima
IPPS
2002
IEEE
14 years 9 days ago
Implementing the NAS Benchmark MG in SAC
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
Clemens Grelck
ISHPC
1999
Springer
13 years 11 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
HPCA
1997
IEEE
13 years 11 months ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross