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IEEEPACT
2000
IEEE
13 years 12 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
CASES
2009
ACM
13 years 5 months ago
Spatial complexity of reversibly computable DAG
In this paper we address the issue of making a program reversible in terms of spatial complexity. Spatial complexity is the amount of memory/register locations required for perfor...
Mouad Bahi, Christine Eisenbeis
EMSOFT
2004
Springer
14 years 27 days ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
LCTRTS
2007
Springer
14 years 1 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
ICFP
2003
ACM
14 years 7 months ago
Iterative-free program analysis
Program analysis is the heart of modern compilers. Most control flow analyses are reduced to the problem of finding a fixed point in a certain transition system, and such fixed po...
Mizuhito Ogawa, Zhenjiang Hu, Isao Sasano