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DCC
2008
IEEE
13 years 9 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
DSN
2008
IEEE
13 years 9 months ago
Detouring: Translating software to circumvent hard faults in simple cores
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
Albert Meixner, Daniel J. Sorin
DAC
2009
ACM
13 years 9 months ago
Way Stealing: cache-assisted automatic instruction set extensions
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
SPAA
2010
ACM
13 years 8 months ago
A universal construction for wait-free transaction friendly data structures
Given the sequential implementation of any data structure, we show how to obtain an efficient, wait-free implementation of that data structure shared by any fixed number of proces...
Phong Chuong, Faith Ellen, Vijaya Ramachandran
GRID
2007
Springer
13 years 7 months ago
Managing Large Scale Data for Earthquake Simulations
The Southern California Earthquake Center digital library publishes scientific data generated by seismic wave propagation simulations. The output from a single simulation may be as...
Marcio Faerman, Reagan Moore, Yifeng Cui, Yuanfang...