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» Register computations on ordinals
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MSCS
2006
58views more  MSCS 2006»
13 years 7 months ago
Ordinal computations
Peter Koepke, Martin Koerwien
ACSC
2004
IEEE
13 years 11 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
IPPS
1996
IEEE
13 years 11 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
DSN
2006
IEEE
14 years 1 months ago
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability
Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to sof...
Jie Hu, Shuai Wang, Sotirios G. Ziavras