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DATE
2009
IEEE
171views Hardware» more  DATE 2009»
14 years 13 days ago
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
EMSOFT
2009
Springer
14 years 13 days ago
Modular static scheduling of synchronous data-flow networks: an efficient symbolic representation
This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flow...
Marc Pouzet, Pascal Raymond
FPL
2006
Springer
140views Hardware» more  FPL 2006»
14 years 7 days ago
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications
Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, Field Programmable Gate Arrays (FPGAs) are capable of heating beyond their designed...
Phillip H. Jones, John W. Lockwood, Young H. Cho
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
14 years 5 days ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
CCS
2008
ACM
13 years 10 months ago
SNAPP: stateless network-authenticated path pinning
This paper examines a new building block for next-generation networks: SNAPP, or Stateless Network-Authenticated Path Pinning. SNAPP-enabled routers securely embed their routing d...
Bryan Parno, Adrian Perrig, Dave Andersen