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IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
HIPEAC
2009
Springer
13 years 11 months ago
MPSoC Design Using Application-Specific Architecturally Visible Communication
Abstract. This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide highthroughput communication for str...
Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo ...
IPPS
2010
IEEE
13 years 5 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
SIGOPS
2011
210views Hardware» more  SIGOPS 2011»
13 years 2 months ago
Small trusted primitives for dependable systems
Secure, fault-tolerant distributed systems are difficult to build, to validate, and to operate. Conservative design for such systems dictates that their security and fault toleran...
Petros Maniatis, Byung-Gon Chun
ICS
2011
Tsinghua U.
12 years 11 months ago
High performance linpack benchmark: a fault tolerant implementation without checkpointing
The probability that a failure will occur before the end of the computation increases as the number of processors used in a high performance computing application increases. For l...
Teresa Davies, Christer Karlsson, Hui Liu, Chong D...