1179 search results - page 64 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
135
Voted
ITC
1999
IEEE
15 years 8 months ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
121
Voted
AIPS
2006
15 years 5 months ago
2006
Reasoning on precedence relations is crucial for many planning and scheduling systems. In this paper we propose a double precedence graph where direct precedence relations are kep...
134
Voted
CORR
2011
Springer
14 years 10 months ago
2011
Springer
Abstract. Most instruments - formalisms, concepts, and metrics for social networks analysis fail to capture their dynamics. Typical systems exhibit different scales of dynamics, ra...
165
Voted
PRESENCE
2007
15 years 3 months ago
2007
We describe a methodology for Virtual Reality designers to capture and resynthesize the variations in sound made by objects when we interact with them through contact such as touc...
137
Voted
GLVLSI
2008
IEEE
15 years 3 months ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...