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RECONFIG
2009
IEEE
118views VLSI» more  RECONFIG 2009»
14 years 3 months ago
Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations
Abstract. Protecting an implementation against Side Channel Analysis for Reverse Engineering (SCARE) attacks is a great challenge and we address this challenge by presenting a fir...
Julien Bringer, Hervé Chabanne, Jean-Luc Da...
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 3 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
IPPS
2006
IEEE
14 years 2 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
INFOSCALE
2006
ACM
14 years 2 months ago
Scalable hardware accelerator for comparing DNA and protein sequences
Abstract— Comparing genetic sequences is a well-known problem in bioinformatics. Newly determined sequences are being compared to known sequences stored in databases in order to ...
Philippe Faes, Bram Minnaert, Mark Christiaens, Er...
ISI
2005
Springer
14 years 2 months ago
Performance Study of a Compiler/Hardware Approach to Embedded Systems Security
Abstract. Trusted software execution, prevention of code and data tampering, authentication, and providing a secure environment for software are some of the most important security...
Kripashankar Mohan, Bhagirath Narahari, Rahul Simh...