74 search results - page 4 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
VTS
2003
IEEE
14 years 18 days ago
2003
IEEE
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
VTS
2008
IEEE
14 years 1 months ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
NIPS
1996
13 years 8 months ago
1996
We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decod...
ITC
2002
IEEE
14 years 8 days ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
EH
2003
IEEE
14 years 19 days ago
2003
IEEE
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...