74 search results - page 7 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
PDP
2003
IEEE
14 years 19 days ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
VLSISP
2010
13 years 5 months ago
2010
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
DAC
2004
ACM
14 years 24 days ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
TNN
2008
13 years 6 months ago
2008
Abstract--This paper investigates whether spike-timing-dependent plasticity (STDP) can minimize the effect of mismatch within the context of a depth-from-motion algorithm. To impro...