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IJCSS
2007
133views more  IJCSS 2007»
13 years 9 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
14 years 1 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar
JAIR
2006
179views more  JAIR 2006»
13 years 9 months ago
The Fast Downward Planning System
Fast Downward is a classical planning system based on heuristic search. It can deal with general deterministic planning problems encoded in the propositional fragment of PDDL2.2, ...
Malte Helmert
ICCV
2011
IEEE
12 years 9 months ago
The Power of Comparative Reasoning
Rank correlation measures are known for their resilience to perturbations in numeric values and are widely used in many evaluation metrics. Such ordinal measures have rarely been ...
Jay Yagnik, Dennis Strelow, David Ross, Ruei-sung ...
BMCBI
2010
227views more  BMCBI 2010»
13 years 10 months ago
Accurate and efficient gp120 V3 loop structure based models for the determination of HIV-1 co-receptor usage
Background: HIV-1 targets human cells expressing both the CD4 receptor, which binds the viral envelope glycoprotein gp120, as well as either the CCR5 (R5) or CXCR4 (X4) co-recepto...
Majid Masso, Iosif I. Vaisman