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» Representational Reasoning and Verification
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ATVA
2006
Springer
140views Hardware» more  ATVA 2006»
14 years 17 days ago
On the Construction of Fine Automata for Safety Properties
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. Each safety property can be associated with...
Orna Kupferman, Robby Lampert
LPAR
2010
Springer
13 years 6 months ago
Dafny: An Automatic Program Verifier for Functional Correctness
Traditionally, the full verification of a program's functional correctness has been obtained with pen and paper or with interactive proof assistants, whereas only reduced ver...
K. Rustan M. Leino
CADE
2007
Springer
14 years 9 months ago
Solving Quantified Verification Conditions Using Satisfiability Modulo Theories
Abstract. First order logic provides a convenient formalism for describing a wide variety of verification conditions. Two main approaches to checking such conditions are pure first...
Yeting Ge, Clark Barrett, Cesare Tinelli
GLVLSI
2002
IEEE
160views VLSI» more  GLVLSI 2002»
14 years 1 months ago
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Spectral techniques have found many applications in computeraided design, including synthesis, verification, and testing. Decision diagram representations permit spectral coeffici...
Whitney J. Townsend, Mitchell A. Thornton, Rolf Dr...
ATAL
2004
Springer
14 years 17 days ago
Automated Conversion and Simplification of Plan Representations
As planning agents grow more sophisticated, issues of plan representation arise alongside concerns with plan generation. Planning methods work over increasingly large and difficul...
Martin Allen, Shlomo Zilberstein