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EUROPAR
2010
Springer
13 years 10 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
CN
2002
102views more  CN 2002»
13 years 9 months ago
Predicting bottleneck bandwidth sharing by generalized TCP flows
The paper presents a technique for computing the individual throughputs and the average queue occupancy when multiple TCP connections share a single bottleneck buffer. The bottlene...
Archan Misra, Teunis J. Ott, John S. Baras
EWC
2008
117views more  EWC 2008»
13 years 9 months ago
Performance of parallel computations with dynamic processor allocation
In parallel adaptive mesh refinement (AMR) computations the problem size can vary significantly during a simulation. The goal here is to explore the performance implications of dyn...
Saeed Iqbal, Graham F. Carey
IPPS
2010
IEEE
13 years 7 months ago
Oversubscription on multicore processors
Abstract: Existing multicore systems already provide deep levels of thread parallelism. Hybrid programming models and composability of parallel libraries are very active areas of r...
Costin Iancu, Steven Hofmeyr, Filip Blagojevic, Yi...
JSAC
2007
127views more  JSAC 2007»
13 years 9 months ago
Mechanism-based resource allocation for multimedia transmission over spectrum agile wireless networks
— We propose to add a new dimension to existing wireless multimedia systems by enabling autonomous stations to dynamically compete for communication resources through adjustment ...
Ahmad Reza Fattahi, Fangwen Fu, Mihaela van der Sc...