Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
The paper presents a technique for computing the individual throughputs and the average queue occupancy when multiple TCP connections share a single bottleneck buffer. The bottlene...
In parallel adaptive mesh refinement (AMR) computations the problem size can vary significantly during a simulation. The goal here is to explore the performance implications of dyn...
Abstract: Existing multicore systems already provide deep levels of thread parallelism. Hybrid programming models and composability of parallel libraries are very active areas of r...
Costin Iancu, Steven Hofmeyr, Filip Blagojevic, Yi...
— We propose to add a new dimension to existing wireless multimedia systems by enabling autonomous stations to dynamically compete for communication resources through adjustment ...
Ahmad Reza Fattahi, Fangwen Fu, Mihaela van der Sc...