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» Reuse Technique in Hardware Design
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CHARME
2005
Springer
136views Hardware» more  CHARME 2005»
15 years 11 months ago
Acceleration of SAT-Based Iterative Property Checking
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
Daniel Große, Rolf Drechsler
ER
2000
Springer
186views Database» more  ER 2000»
15 years 9 months ago
Conceptual Design of Electronic Product Catalogs Using Object-Oriented Hypermedia Modeling Techniques
The application of conceptual models that assure both the consistency and usability of Electronic Product Catalogs (EPC's) is a main concern in the e-commerce community, mainl...
Cristina Cachero, Jaime Gómez, Oscar Pastor
CASES
2006
ACM
15 years 9 months ago
Incremental elaboration for run-time reconfigurable hardware designs
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
Arran Derbyshire, Tobias Becker, Wayne Luk
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
16 years 10 days ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
DAC
2005
ACM
15 years 8 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim