Sciweavers

2778 search results - page 529 / 556
» Reuse Technique in Hardware Design
Sort
View
ASPLOS
2009
ACM
14 years 8 months ago
Dynamic prediction of collection yield for managed runtimes
The growth in complexity of modern systems makes it increasingly difficult to extract high-performance. The software stacks for such systems typically consist of multiple layers a...
Michal Wegiel, Chandra Krintz
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
14 years 4 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
14 years 4 months ago
Post-routing redundant via insertion and line end extension with via density consideration
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 4 months ago
A spectrally accurate integral equation solver for molecular surface electrostatics
Electrostatic analysis of complicated molecular surfaces arises in a number of nanotechnology applications including: biomolecule design, carbon nanotube simulation, and molecular...
Shih-Hsien Kuo, Jacob White
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...