2778 search results - page 532 / 556 » Reuse Technique in Hardware Design |
ISCA
2005
IEEE
14 years 28 days ago
2005
IEEE
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
MICRO
2005
IEEE
14 years 28 days ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
ITC
2003
IEEE
14 years 19 days ago
2003
IEEE
Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurren...
ITC
2003
IEEE
14 years 19 days ago
2003
IEEE
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
FCCM
2002
IEEE
14 years 9 days ago
2002
IEEE
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...