2778 search results - page 550 / 556 » Reuse Technique in Hardware Design |
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
DSN
2006
IEEE
14 years 23 days ago
2006
IEEE
The growing computational and storage needs of several scientific applications mandate the deployment of extreme-scale parallel machines, such as IBM’s BlueGene/L which can acc...
ISCAS
2006
IEEE
14 years 22 days ago
2006
IEEE
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...