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145
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
148
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
146
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
119
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
122
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IISWC
2006
IEEE
15 years 10 months ago
2006
IEEE
— Understanding the behavior of emerging workloads is important for designing next generation microprocessors. For addressing this issue, computer architects and performance anal...