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ISSS
1998
IEEE
152views Hardware» more  ISSS 1998»
14 years 2 months ago
Code Generation for Compiled Bit-True Simulation of DSP Applications
Bit-true simulation veri es the nite word length choices in the VLSI implementation of a DSP application. Present-day bit-true simulation tools are time consuming. We elaborate a ...
Luc De Coster, Marleen Adé, Rudy Lauwereins...
VLSID
1996
IEEE
130views VLSI» more  VLSID 1996»
14 years 2 months ago
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents ...
S. Ramanathan, V. Visvanathan
ATVA
2004
Springer
115views Hardware» more  ATVA 2004»
14 years 1 months ago
First-Order LTL Model Checking Using MDGs
In this paper, we describe a first-order linear time temporal logic (LTL) model checker based on multiway decision graphs (MDG). We developed a first-order temporal language, LMDG ...
Fang Wang, Sofiène Tahar, Otmane Aït M...
NAACL
2003
13 years 11 months ago
Unsupervised Learning of Morphology for English and Inuktitut
We describe a simple unsupervised technique for learning morphology by identifying hubs in an automaton. For our purposes, a hub is a node in a graph with in-degree greater than o...
Howard Johnson, Joel D. Martin
SGP
2003
13 years 11 months ago
Stellar Subdivision Grammars
In this paper we develop a new description for subdivision surfaces based on a graph grammar formalism. Subdivision schemes are specified by a context sensitive grammar in which ...
Luiz Velho