Sciweavers

93 search results - page 17 / 19
» Routers with Very Small Buffers
Sort
View
ANCS
2009
ACM
13 years 6 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
LCTRTS
2009
Springer
14 years 3 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
INFOCOM
2005
IEEE
14 years 2 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas
INFOCOM
2003
IEEE
14 years 1 months ago
Exploring the trade-off between label size and stack depth in MPLS Routing
— Multiprotocol Label Switching or MPLS technology is being increasingly deployed by several of the largest Internet service providers to solve problems such as traffic engineer...
Anupam Gupta, Amit Kumar, Rajeev Rastogi
INFOCOM
2003
IEEE
14 years 1 months ago
On Guaranteed Smooth Scheduling For Input-Queued Switches
— Input-queued switches are used extensively in the design of high-speed routers. As switch speeds and sizes increase, the design of the switch scheduler becomes a primary challe...
Isaac Keslassy, Murali S. Kodialam, T. V. Lakshman...