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» Run-time Optimization for Pipelined Systems
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FPGA
2009
ACM
343views FPGA» more  FPGA 2009»
14 years 2 months ago
Fpga-based face detection system using Haar classifiers
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kas...
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 4 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
HPCA
2000
IEEE
14 years 13 hour ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
ISVLSI
2002
IEEE
89views VLSI» more  ISVLSI 2002»
14 years 15 days ago
Speedup of Self-Timed Digital Systems Using Early Completion
An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their s...
Scott C. Smith
ISVC
2009
Springer
14 years 2 months ago
LightShop: An Interactive Lighting System Incorporating the 2D Image Editing Paradigm
Lighting is a fundamental and important process in the 3D animation pipeline. Conventional lighting workflow is time-consuming and labor-intensive. A user must fiddle with a rang...
Younghui Kim, Junyong Noh