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» Runtime Verification Using a Temporal Description Logic
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CAV
1998
Springer
138views Hardware» more  CAV 1998»
14 years 1 days ago
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
bstract description of state machines (ASMs), in which data and data operations are d using abstract sort and uninterpreted function symbols. ASMs are suitable for describing Regis...
Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Core...
FSTTCS
2006
Springer
13 years 11 months ago
Monitoring of Real-Time Properties
This paper presents a construction for runtime monitors that check real-time properties expressed in timed LTL (TLTL). Due to D'Souza's results, TLTL can be considered a ...
Andreas Bauer 0002, Martin Leucker, Christian Scha...
IJCAI
2007
13 years 9 months ago
A Description Logic of Change
We combine the modal logic S5 with the description logic (DL) ALCQI. In this way, we obtain a multi-dimensional DL, S5ALCQI, whose purpose is reasoning about change. S5ALCQI is ca...
Alessandro Artale, Carsten Lutz, David Toman
FORMATS
2010
Springer
13 years 5 months ago
Robust Satisfaction of Temporal Logic over Real-Valued Signals
Abstract. We consider temporal logic formulae specifying constraints in continuous time and space on the behaviors of continuous and hybrid dynamical system admitting uncertain par...
Alexandre Donzé, Oded Maler
ECAI
2008
Springer
13 years 9 months ago
Temporal Logic Patterns for Querying Qualitative Models of Genetic Regulatory Networks
Formal verification based on model checking provides a powerful technology to query qualitative models of dynamical systems. The application of model-checking approaches is hamper...
Pedro T. Monteiro, Delphine Ropers, Radu Mateescu,...