252 search results - page 23 / 51 » Runtime Verification Using a Temporal Description Logic |
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
APLAS
2004
ACM
13 years 11 months ago
2004
ACM
This paper shows how type effect systems can be combined with model-checking techniques to produce powerful, automatically verifiable program logics for higher-order programs. The ...
KBSE
1999
IEEE
14 years 3 days ago
1999
IEEE
This paper describes the application of advanced formal modelling techniques and tools from the CADP toolset to the verification of CFS, a distributed file system kernel. After a ...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
VLSID
1999
IEEE
14 years 2 days ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...