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» Runtime Verification Using a Temporal Description Logic
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MEMOCODE
2010
IEEE
13 years 5 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
CAISE
2008
Springer
13 years 9 months ago
Formal Modeling and Discrete-Time Analysis of BPEL Web Services
Abstract. Web services are increasingly used for building enterprise information systems according to the Service Oriented Architecture (Soa) paradigm. We propose in this paper a t...
Radu Mateescu, Sylvain Rampacek
ISCIS
2004
Springer
14 years 1 months ago
Semi-formal and Formal Models Applied to Flexible Manufacturing Systems
Abstract. Flexible Manufacturing Systems (FMSs) are adopted to process different goods in different mix ratios allowing firms to react quickly and efficiently to changes in produ...
Andrea Matta, Carlo A. Furia, Matteo Rossi
IBPRIA
2007
Springer
13 years 9 months ago
Automatic Learning of Conceptual Knowledge in Image Sequences for Human Behavior Interpretation
This work describes an approach for the interpretation and explanation of human behavior in image sequences, within the context of a Cognitive Vision System. The information source...
Pau Baiget, Carles Fernández Tena, F. Xavie...
ENTCS
2007
130views more  ENTCS 2007»
13 years 7 months ago
Specify, Compile, Run: Hardware from PSL
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
Roderick Bloem, Stefan Galler, Barbara Jobstmann, ...