1642 search results - page 257 / 329 » SPINning Parallel Systems Software |
HICSS
1995
IEEE
14 years 18 days ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
HCI
2007
13 years 10 months ago
2007
This paper discusses the use of cognitive models as augmented metacognition on task allocation for tasks requiring visual attention. In the domain of naval warfare, the complex and...
CCGRID
2002
IEEE
14 years 2 months ago
2002
IEEE
Despite the large research efforts in the SW–DSM community, this technology has not yet been adapted widely for significant codes beyond benchmark suites. One of the reasons co...
ICS
2010
Tsinghua U.
13 years 11 months ago
2010
Tsinghua U.
As the number of I/O-intensive MPI programs becomes increasingly large, many efforts have been made to improve I/O performance, on both software and architecture sides. On the sof...
MICRO
1997
IEEE
14 years 1 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...