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» Safe programmable speculative parallelism
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VLDB
2005
ACM
113views Database» more  VLDB 2005»
14 years 3 months ago
Optimistic Intra-Transaction Parallelism on Chip Multiprocessors
With the advent of chip multiprocessors, exploiting intra-transaction parallelism is an attractive way of improving transaction performance. However, exploiting intra-transaction ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...
PPOPP
2006
ACM
14 years 3 months ago
POSH: a TLS compiler that exploits program structure
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better understood, it is important to focus on TLS compilation. TLS compilers are interesting in that,...
Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin ...
ICS
2003
Tsinghua U.
14 years 3 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
ASPLOS
2004
ACM
14 years 3 months ago
Coherence decoupling: making use of incoherence
This paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol ...
Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar ...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 4 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta