2020 search results - page 11 / 404 » Scalable Instruction-Level Parallelism. |
ICS
1995
Tsinghua U.
14 years 10 days ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
CAMP
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
ICS
2011
Tsinghua U.
13 years 7 days ago
2011
Tsinghua U.
Applications must scale well to make efficient use of even medium-scale parallel systems. Because scaling problems are often difficult to diagnose, there is a critical need for sc...
ICMCS
2006
IEEE
14 years 2 months ago
2006
IEEE
The MISP Processor is a programmable media processor which supports multi-issuing, multi-threading and stream processing techniques. MISP executes applications that have been mapp...
ANSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Programs often call the same function with the same arguments, yielding the same results. We call this phenomenon, “function reuse”. Previously, we have shown such a behavior ...