770 search results - page 49 / 154 » Scalable stochastic processors |
CDES
2008
14 years 11 days ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
EOR
2007
13 years 11 months ago
2007
In this paper, we suggest a parallel algorithm based on a shared memory SIMD architecture for solving an n item subset-sum problem in time O(2n/2 /p) by using p = 2q processors, 0...
SC
2004
ACM
14 years 4 months ago
2004
ACM
We describe an innovative highly parallel application program, ParaDiS, which computes the plastic strength of materials by tracing the evolution of dislocation lines over time. W...
IBMRD
2006
13 years 11 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
EUROMICRO
1997
IEEE
14 years 3 months ago
1997
IEEE
CMOS technology should, over the next few years, reach lithography of under 0.1¡ . This provides a die area improvement of a factor of 10 over today’s technology. What is the b...