Sciweavers

79 search results - page 15 / 16
» Scalably Scheduling Power-Heterogeneous Processors
Sort
View
MICRO
2005
IEEE
114views Hardware» more  MICRO 2005»
14 years 29 days ago
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
Sam S. Stone, Kevin M. Woley, Matthew I. Frank
AGENTS
2000
Springer
13 years 11 months ago
Tools for Developing and Monitoring Agents in Distributed Multi-Agent Systems
Before the powerful agent programming paradigm can be adopted in commercial or industrial settings, a complete environment, similar to that for other programming languages, must b...
John R. Graham, Daniel McHugh, Michael Mersic, Fos...
LCTRTS
2001
Springer
13 years 12 months ago
Evaluating and Optimizing Thread Pool Strategies for Real-Time CORBA
Strict control over the scheduling and execution of processor resources is essential for many fixed-priority real-time applications. To facilitate this common requirement, the Re...
Irfan Pyarali, Marina Spivak, Ron Cytron, Douglas ...
ICFP
2010
ACM
13 years 8 months ago
Lazy tree splitting
Nested data-parallelism (NDP) is a declarative style for programming irregular parallel applications. NDP languages provide language features favoring the NDP style, efficient com...
Lars Bergstrom, Mike Rainey, John H. Reppy, Adam S...
JEC
2006
100views more  JEC 2006»
13 years 7 months ago
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications
During the last two decades, Single Instruction Multiple Data (SIMD) processors have become important architectures in embedded systems for image processing applications. The main ...
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Ba...