860 search results - page 56 / 172 » Scaling Up Software Architecture Evaluation Processes |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
IPPS
2002
IEEE
14 years 21 days ago
2002
IEEE
Short vector SIMD instructions on recent microprocessors, such as SSE on Pentium III and 4, speed up code but are a major challenge to software developers. We present a compiler t...
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
ICSE
2007
IEEE-ACM
14 years 7 months ago
2007
IEEE-ACM
Database-centric information systems are critical to the operations of large organisations. In particular, they often process a large amount of data with stringent performance req...
EUROPAR
2007
Springer
13 years 11 months ago
2007
Springer
Due to the increasing performance requirements of decoding H.264/AVC in HDTV or larger resolutions, new approaches are necessary to enable real-time processing. According to the cu...