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VLSISP
1998
128views more  VLSISP 1998»
13 years 9 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
TPDS
2002
105views more  TPDS 2002»
13 years 9 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
ARC
2012
Springer
317views Hardware» more  ARC 2012»
12 years 5 months ago
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
Abid Rafique, Nachiket Kapre, George A. Constantin...
APCSAC
2005
IEEE
14 years 2 months ago
Speculative Issue Logic
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
You-Jan Tsai, Jong-Jiann Shieh
GCC
2007
Springer
14 years 3 months ago
Adapting to Application Workflow in Processing Data Integration Queries
Data integration has evolved to provide efficient data management across distributed and heterogeneous data sources in grid environment. However, existing works in data integratio...
Yongwei Wu, Jia Liu, Gang Chen, Guangwen Yang, Bo ...