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ISCAPDCS
2004
13 years 9 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
JPDC
2006
185views more  JPDC 2006»
13 years 7 months ago
Commodity cluster-based parallel processing of hyperspectral imagery
The rapid development of space and computer technologies has made possible to store a large amount of remotely sensed image data, collected from heterogeneous sources. In particul...
Antonio Plaza, David Valencia, Javier Plaza, Pablo...
JSA
2008
124views more  JSA 2008»
13 years 7 months ago
Processor array architectures for flexible approximate string matching
In this paper, we present linear processor array architectures for flexible approximate string matching. These architectures are based on parallel realization of dynamic programmi...
Panagiotis D. Michailidis, Konstantinos G. Margari...
CCGRID
2001
IEEE
13 years 11 months ago
TACO-Exploiting Cluster Networks for High-Level Collective Operations
TACO (Topologies and Collections) is a template library that introduces the flavour of distributed data parallel processing by means of reusable topology classes and C++ s. This p...
Jörg Nolte, Mitsuhisa Sato, Yutaka Ishikawa
IPPS
1998
IEEE
14 years 1 days ago
A Scalable VLSI Architecture for Binary Prefix Sums
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...