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JCST
2008
140views more  JCST 2008»
13 years 9 months ago
ROPAS: Cross-Layer Cognitive Architecture for Mobile UWB Networks
The allocation of bandwidth to unlicensed users, without significantly increasing the interference on the existing licensed users, is a challenge for Ultra Wideband (UWB) networks....
Chittabrata Ghosh, Bin Xie, Dharma P. Agrawal
TOMACS
1998
140views more  TOMACS 1998»
13 years 9 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
JSA
2000
116views more  JSA 2000»
13 years 9 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
14 years 4 months ago
A dual-core programmable decoder for LDPC convolutional codes
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
Marcos B. S. Tavares, Emil Matús, Steffen K...
SIGIR
2006
ACM
14 years 3 months ago
Load balancing for term-distributed parallel retrieval
Large-scale web and text retrieval systems deal with amounts of data that greatly exceed the capacity of any single machine. To handle the necessary data volumes and query through...
Alistair Moffat, William Webber, Justin Zobel