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ASAP
1997
IEEE
144views Hardware» more  ASAP 1997»
13 years 12 months ago
Automatic data mapping of signal processing applications
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...
Corinne Ancourt, Denis Barthou, Christophe Guettie...
RTAS
2005
IEEE
14 years 1 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
13 years 11 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
RTCSA
2005
IEEE
14 years 1 months ago
Approximation Algorithms for Scheduling Multiple Feasible Interval Jobs
Abstract— Time-critical jobs in many real-time applications have multiple feasible intervals. Such a job is constrained to execute from start to completion in one of its feasible...
Jian-Jia Chen, Jun Wu, Chi-Sheng Shih, Tei-Wei Kuo
RTAS
2005
IEEE
14 years 1 months ago
Improving WCET by Optimizing Worst-Case Paths
It is advantageous to perform compiler optimizations to lower the WCET of a task since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compi...
Wankang Zhao, William C. Kreahling, David B. Whall...