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IFIP
2004
Springer
14 years 24 days ago
The Inherent Queuing Delay of Parallel Packet Switches
The parallel packet switch (PPS) extends the inverse multiplexing architecture, and is extensively used as the core of contemporary commercial switches. A key factor in the perfor...
Hagit Attiya, David Hay
HOTI
2005
IEEE
14 years 1 months ago
Addressing Queuing Bottlenecks at High Speeds
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley
INFOCOM
2000
IEEE
13 years 11 months ago
On the Stability of Input-Buffer Cell Switches with Speed-Up
— We consider cell-based switch architectures, whose internal switching matrix does not provide enough speed to avoid input buffering. These architectures require a scheduling al...
Marco Ajmone Marsan, Emilio Leonardi, Marco Mellia...
INFOCOM
2005
IEEE
14 years 1 months ago
Practical algorithms for performance guarantees in buffered crossbars
— This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input...
Shang-Tse Chuang, Sundar Iyer, Nick McKeown
IPPS
2008
IEEE
14 years 1 months ago
Providing flow based performance guarantees for buffered crossbar switches
Buffered crossbar switches are a special type of combined input-output queued switches with each crosspoint of the crossbar having small on-chip buffers. The introduction of cross...
Deng Pan, Yuanyuan Yang