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» Secure Configuration of Field Programmable Gate Arrays
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IPPS
2006
IEEE
14 years 1 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
TRIDENTCOM
2006
IEEE
14 years 1 months ago
Light-trail testbed for metro optical networks
— Telecommunication networks have rapidly added staggering amounts of capacity to their long haul networks at low costs per bit using DWDM technologies. Concurrently, there has b...
Nathan A. VanderHorn, Srivatsan Balasubramanian, M...
INFOSCALE
2006
ACM
14 years 1 months ago
Scalable hardware accelerator for comparing DNA and protein sequences
Abstract— Comparing genetic sequences is a well-known problem in bioinformatics. Newly determined sequences are being compared to known sequences stored in databases in order to ...
Philippe Faes, Bram Minnaert, Mark Christiaens, Er...
ACIVS
2005
Springer
14 years 1 months ago
FPGA Design and Implementation of a Wavelet-Domain Video Denoising System
Multiresolution video denoising is becoming an increasingly popular research topic over recent years. Although several wavelet based algorithms reportedly outperform classical sing...
Mihajlo Katona, Aleksandra Pizurica, Nikola Teslic...
FPGA
2010
ACM
294views FPGA» more  FPGA 2010»
14 years 23 days ago
Axel: a heterogeneous cluster with FPGAs and GPUs
This paper describes a heterogeneous computer cluster called Axel. Axel contains a collection of nodes; each node can include multiple types of accelerators such as FPGAs (Field P...
Kuen Hung Tsoi, Wayne Luk