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» Secure FPGA circuits using controlled placement and routing
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AHS
2006
IEEE
137views Hardware» more  AHS 2006»
14 years 1 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
IFIP
2004
Springer
14 years 25 days ago
Reasoning about Secure Interoperation Using Soft Constraints
Abstract The security of a network configuration is based not just on the security of its individual components and their direct interconnections, but also on the potential for sy...
Stefano Bistarelli, Simon N. Foley, Barry O'Sulliv...
ERSA
2004
192views Hardware» more  ERSA 2004»
13 years 8 months ago
VTSim: A Virtex-II Device Simulator
This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Throu...
Jesse Hunter, Peter Athanas, Cameron Patterson
SLIP
2003
ACM
14 years 21 days ago
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
Navaratnasothie Selvakkumaran, Phiroze N. Parakh, ...
DAC
2009
ACM
14 years 8 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang