Sciweavers

1210 search results - page 23 / 242
» Secure Logic Synthesis
Sort
View
ICCAD
1998
IEEE
153views Hardware» more  ICCAD 1998»
13 years 12 months ago
Intellectual property protection by watermarking combinational logic synthesis solutions
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak,...
SAT
2007
Springer
121views Hardware» more  SAT 2007»
14 years 1 months ago
Applying Logic Synthesis for Speeding Up SAT
SAT solvers are often challenged with very hard problems that remain unsolved after hours of CPU time. The research community meets the challenge in two ways: (1) by improving the ...
Niklas Eén, Alan Mishchenko, Niklas Sö...
ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Decomposition based approach for synthesis of multi-level threshold logic circuits
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
Tejaswi Gowda, Sarma B. K. Vrudhula
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
14 years 8 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
FPGA
2009
ACM
148views FPGA» more  FPGA 2009»
14 years 2 months ago
SmartOpt: an industrial strength framework for logic synthesis
In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research i...
Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, ...