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    ICCAD
    1995
    IEEE
    134views Hardware» more  ICCAD 1995»
    A delay model for logic synthesis of continuously-sized networks
    14 years 1 months ago
    A delay model for logic synthesis of continuously-sized networks
    Download  www.cs.york.ac.uk
    ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
    Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
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    DAC
    2008
    ACM
    149views Computer Architecture» more  DAC 2008»
    Automatic synthesis of clock gating logic with controlled netlist perturbation
    14 years 11 months ago
    Automatic synthesis of clock gating logic with controlled netlist perturbation
    Download  www.eecs.berkeley.edu
    Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
    Aaron P. Hurst
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    DATE
    2009
    IEEE
    141views Hardware» more  DATE 2009»
    Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
    14 years 4 months ago
    Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
    Download  www.date-conference.com
    – The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
    Shashikanth Bobba, Jie Zhang, Antonio Pullini, Dav...
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    ITC
    1995
    IEEE
    104views Hardware» more  ITC 1995»
    Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
    14 years 1 months ago
    Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
    Download  www-crc.stanford.edu
    During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
    Nur A. Touba, Edward J. McCluskey
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    CSREAESA
    2006
    109views Embedded Systems» more  CSREAESA 2006»
    Delay-Reduced Combinational Logic Synthesis using Multiplexers
    13 years 11 months ago
    Delay-Reduced Combinational Logic Synthesis using Multiplexers
    Download  ww1.ucmss.com
    - This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
    Rekha K. James, T. K. Shahana, K. Poulose Jacob, S...
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