1210 search results - page 77 / 242 » Secure Logic Synthesis |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
KI
2007
Springer
14 years 4 months ago
2007
Springer
Abstract. We compare three systems for the task of synthesising functional recursive programs, namely Adate, an approach through evolutionary computation, the classification learn...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
VTS
2005
IEEE
14 years 3 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
ASYNC
2003
IEEE
14 years 3 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...