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CGO
2004
IEEE
14 years 20 days ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
CC
2008
Springer
193views System Software» more  CC 2008»
13 years 11 months ago
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model
The polyhedral model provides powerful abstractions to optimize loop nests with regular accesses. Affine transformations in this model capture a complex sequence of execution-reord...
Uday Bondhugula, Muthu Manikandan Baskaran, Sriram...
BMCBI
2010
143views more  BMCBI 2010»
13 years 9 months ago
ETE: a python Environment for Tree Exploration
Background: Many bioinformatics analyses, ranging from gene clustering to phylogenetics, produce hierarchical trees as their main result. These are used to represent the relations...
Jaime Huerta-Cepas, Joaquín Dopazo, Toni Ga...
BMCBI
2008
135views more  BMCBI 2008»
13 years 9 months ago
Ab-origin: an enhanced tool to identify the sourcing gene segments in germline for rearranged antibodies
Background: In the adaptive immune system, variable regions of immunoglobulin (IG) are encoded by random recombination of variable (V), diversity (D), and joining (J) gene segment...
Xiaojing Wang, Di Wu, SiYuan Zheng, Jing Sun, Lin ...
JISE
1998
84views more  JISE 1998»
13 years 8 months ago
Determining the Idle Time of a Tiling: New Results
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. We build upon recent results by ...
Frederic Desprez, Jack Dongarra, Fabrice Rastello,...