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IJPP
2006
99views more  IJPP 2006»
13 years 7 months ago
Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies
Sylvain Girbal, Nicolas Vasilache, Cédric B...
IPPS
1999
IEEE
13 years 11 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ICS
2009
Tsinghua U.
14 years 2 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...