115 search results - page 12 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
FMCAD
2004
Springer
13 years 11 months ago
2004
Springer
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
ENTCS
2006
13 years 7 months ago
2006
Partially Ordered Symbolic Automata (POSAs) are used as the semantical foundation of visual formalisms like the scenario based language of Live Sequence Charts (LSCs). To check whe...
CADE
2008
Springer
14 years 8 months ago
2008
Springer
Abstract. We introduce the notion of array-based system as a suittraction of infinite state systems such as broadcast protocols or sorting programs. By using a class of quantified-...
EMSOFT
2008
Springer
13 years 9 months ago
2008
Springer
Runtime property checking (as implemented in tools like Purify or Valgrind) checks whether a program execution satisfies a property. Active property checking extends runtime check...