115 search results - page 17 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
IFM
2009
Springer
14 years 2 months ago
2009
Springer
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
SPIN
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
ENTCS
2002
13 years 7 months ago
2002
We report on the automatic verification of timed probabilistic properties of the IEEE 1394 root contention protocol combining two existing tools: the real-time modelchecker Kronos...
DSN
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper introduces SymPLFIED, a program-level framework which allows specification of arbitrary error detectors and the verification of their efficacy against hardware errors. ...