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» Sequential Circuits for Relational Analysis
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ICCAD
2007
IEEE
165views Hardware» more  ICCAD 2007»
14 years 1 months ago
Automated refinement checking of concurrent systems
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
CORR
2010
Springer
198views Education» more  CORR 2010»
13 years 9 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
TCAD
2010
121views more  TCAD 2010»
13 years 3 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
DAC
2009
ACM
14 years 10 months ago
Improving testability and soft-error resilience through retiming
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
TACAS
2010
Springer
191views Algorithms» more  TACAS 2010»
14 years 4 months ago
Blocked Clause Elimination
Boolean satisfiability (SAT) and its extensions are becoming a core technology for the analysis of systems. The SAT-based approach divides into three steps: encoding, preprocessin...
Matti Järvisalo, Armin Biere, Marijn Heule